The technology disclosed relates to high-density integrated circuits. In particular, the technology disclosed relates to the fabrication of memory cells and their associated peripheral circuits in integrated circuit devices that include non-volatile memory.
There is a present need to increase the operational speed of non-volatile memory devices. To accomplish this, various techniques have been implemented in device processing and structural designs. For example, reducing the feature dimensions of non-volatile memory devices typically increases their operational speed. Another way of accomplishing this involves reducing the spacing between the memory cell control gates by fabricating bit lines that may serve as transistor sources and/or drains. The operational speed of non-volatile memory devices has also been increased by minimizing the spacing between contacts. Siliciding the gate structures of a memory array has also increased operational speed by reducing gate electrical resistance, thus reducing response delays. In some cases, siliciding has been achieved by employing a self-aligned process referred to in the art as saliciding.
Bit line shorting as a result of a salicide process has been a problem in some prior art manufacturing processes. For example, U.S. Pat. No. 6,566,194, issued May 20, 2003, discloses “processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the method, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. According to another aspect of the method, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines.” (U.S. Pat. No. 6,566,194, Abstract)
U.S. Pat. No. 6,136,636, issued Oct. 24, 2000, discloses a method of reducing resistance in deep sub-micron CMOS transistors by forming ultra-shallow source and drain structures and then forming salicide structures on the exposed substrate and gate.
The difficulties involved in manufacturing non-volatile memory devices are increased by the differing types of circuitry they include. For example, non-volatile memory devices include a memory cell array and various peripheral circuitry functions. The memory cell array includes memory cells having control gates, charge trapping structures such as floating gates or charge trapping dielectrics, and source and drain regions. The control gates can be connected together by word lines. The source and drain regions can be connected in series or in parallel by bit lines. The peripheral circuitry can include field effect transistors adapted for high- or low-voltage operation by use of gate dielectrics with different thicknesses, and can include functions such as decoders, charge pumps and control circuitry to facilitate the programming, reading, and erasing of data in the cells of the memory cell array.
It is desirable to provide memory technology for nonvolatile memory that supports the manufacture of memory arrays, including virtual ground memory arrays, without bit line shorting.